This invention relates to a line change-over technique or that which is effective for application on a semiconductor integrated circuit and to a semi-conductor memory using the same thereon.
In a semiconductor memory like RAM (Random Access Memory), a deterioration of product yield due to an occurrence of defective bits becomes a subject of discussion in accordance with increase of a memory array capacity. In view of the situation above, it has been proposed that a redundancy circuit for relieving the defective bits by replacing a column or a row including defective bits in the memory array with a spare memory column or memory row prepared separately is provided, thereby improving the yield.
We, the inventors, have thought out the circuit shown in FIG. 1 as a line change-over circuit for changing a line of such redundancy circuit and a normal line. That is to say, the line change-over circuit comprises, for example, a programmable state setting means or a state setting circuit 1 constituted of a fuse element F and a resistance R connected in series between a supply voltage V.sub.cc and a ground potential of the circuit as illustrated. A level of a program signal S outputted from the state setting means 1 is determined according to whetehr or not the fuse element F is fused. A pair of N-channel type and P-channel type MOSFET's Q.sub.1, Q.sub.2 kept on or off in a complementary manner each other by the program signal S constitute a transfer gate for transmitting a selection signal .phi..sub.y of a Y decoder 2 selectively. In this configuration, when there is a defective bit present in a memory array (not illustrated), a program of the state setting means 1 is executed. That is, the fuse F of the state setting circuit 1 of state setting means 1 provided at every memory columns which corresponds to the memory column including the defective bit is fused. The MOSFET's Q.sub.1 and Q.sub.2 are turned off and on respectively according to the output level (program signal S) of the programmed state setting means 1. The selection signal .phi..sub.y outputted from the Y decoder 2 for MOSFET's Q.sub.1 and Q.sub.2 being turned off and on respectively is transmitted to a redundancy column switch for selecting a spare redundancy memory column through a line SL instead of being transmitted to a column switch (not illustrated) for connecting a data line of a normal memory column including the defective bit to a common data line. Consequently, the redundancy memory column is selected instead of the normal memory column including the defective bit.
According to this configuration, however, a line (wiring) of which side is cutted off by the program signal S of the state setting means 1 is kept floating. More specifically, in case the state setting means 1 is programmed so as to keep the N-channel type MOSFET Q.sub.1 off and the P-channel type MOSFET Q.sub.2 on, for example, for changing the memory column including the defective bit with a spare redundancy memory column in FIG. 1, a node A is kept floating by having MOSFET Q.sub.1 cut off. In this case, an undesirable coupling which is brought with a stray capacitor between a wiring coupled to the node A and other wiring such as power wiring or the like cannot be neglected. If a potential at the node A kept floating is boosted instantaneously by coupling with a power supply, then a malfunction whereby a column switch of the memory column including a defective bit will be turned on is easy to take place.
The inventors have then thought out that resistors R.sub.1, R.sub.2 of high resistance which are not to exert an influence on level of the pulsing signal .phi..sub.y may be interposed between the normal line and the spare line on redundancy side and the ground potential of the circuit respectively as shown in FIG. 1, thereby fixing the lines forcedly on the ground potential of the circuit when MOSFET Q.sub.1 or Q.sub.2 on the lines is cut off. However, it has been found that the connection of such high resistances R.sub.1, R.sub.2 is still not effective to prevent the voltage floating on each line which is so brought by noise arising from an instantaneous power fluctuation or the like. The inventors have thought out further that a switch MOSFET indicated by Q.sub.3 in the drawing, namely MOSFET Q.sub.3 which is kept on according to a programmed state at the state setting means 1 may be provided, and then the switch MOSFET Q.sub.3 will be turned on to drop a level of the line forcedly down to the ground potential of the circuit. In such method, however, another state setting means for setting on/off state of the switch MOSFET Q.sub.3 will have to be provided separately from the state setting means 1 for changing to the spare redundancy memory column. Be that as it may, a portion to program inevitably increases in accordance with an increase in number of the state setting means as mentioned, which may involve an inconvenience to cause a deterioration of the device yield from insecureness of the program (fuse element being fused or the like).